The present invention generally relates to a very large scale integration (VLSI) circuit as part of an electronic chip which has as its principle application improving personal computer (PC) microprocessor performance by reducing the amount of wait states incurred when accessing dynamic random access memory (DRAM) memory for both read and write accesses.
In earlier generations of PC chips sets, the range of CPU and DRAM speed was more narrow than current generations of chip sets. Chip set designers were making designs to support 80286 processors operating from 6 to 12 MHz. Those systems normally supported affordable dynamic memories with RAS (Row Address Strobe) access times of 120 or 100 ns.
Newer technologies have made available 80286 processors operating up to 25 KHz and 80386DX processors capable of 33 MHz clock rates. The DRAM performance has also improved. Some memory manufactures currently produce DRAMs with access times as low as 50 ns. These new, faster devices have segregated the chip set market between high-, mid-range- and low-end PC systems which is why the present invention incorporates extensive user programmable DRAM interface options into its design. Microprocessor systems normally allow processor clock driven wait states to be inserted within memory access cycles in integer values only (i.e. 0, 1, 2, 3, 4) in order to match performance specifications of various microprocessors, DRAM controller and DRAM device combinations. Although successful in permitting combinations of such devices with differing performance specifications to be used, the method seriously limits the ability of a system to perform to the potential capabilities of modern microprocessors.
Prior art devices permit the programming of memory addressing signals such as Row Address Strobe (RAS) and Column Address Strobe (CAS) but is limited to tying them to the memory cycle start time and to the processor clock.
The present invention is directed to overcoming the prior art limitations with a device which allows RAS and CAS to be decoupled from the exact memory cycle start time and enables signal pulse resolution twice that of the processor clock resulting in significant processor performance gains.